Why Verilog Is Not the End

Verilog is enough to design and simulate real RTL — you proved that across Course 1, from the first AND gate through the Tiny Calculator Engine capstone. What Verilog alone does not give you is a scalable way to check that design once it grows past a handful of signals.

That is the gap SystemVerilog fills. It extends Verilog, keeping everything you know, and adds features for both design and verification. Three verification additions matter most:

• Assertions state a rule once ("these two signals never go high on the same edge") and the simulator checks it automatically, at every clock edge the assertion names, instead of you writing a directed test for every case you can think of.
• Reusable testbench classes let you write verification code once and reuse it across designs, instead of starting from a blank testbench file each time.
• Constrained-random stimulus has the tool pick input values at random, within rules you write, so it reaches combinations a human tester would not think to write by hand. Verilog can already produce random numbers with $random; the rules, and the solver that picks values obeying them, are what SystemVerilog adds.

Course 1 taught you to build RTL and check it with supplied directed tests, whose inputs were chosen in advance. Course 2 (SystemVerilog Verification Essentials) teaches you to write the testbenches that do that checking at scale.