Combinational Logic

In combinational logic the output is determined entirely by the current input values — there is no clock and no memory of earlier inputs, so the same inputs always produce the same output. You describe it in Verilog with continuous assign statements and the gate operators: & for AND, | for OR, ~ for NOT, and ^ for XOR.

Composing gates is a matter of naming intermediate wire signals: one assignment drives a wire, another reads it. A whole combinational block is just inputs flowing through gates and named wires to outputs, with every output driven exactly once.

When a combinational design fails its checks, work through a short list: confirm every output is actually driven, make sure the operator matches the truth table you intended, and check the testbench for an infinite loop or unbounded stimulus that could make a run hang. Most early failures are one of these three.