Numbers in Hardware

In Verilog, a signal can be a single bit or a vector of bits. [3:0] declares four bits, numbered 3 down to 0, with bit 3 as the most significant bit (MSB) and bit 0 as the least significant. Hex is just a compact way to write a vector: 4'hD means a 4-bit value equal to 4'b1101, which is 13 in decimal.

The important habit for hardware is that width is fixed. A wire that is four bits wide can only hold four bits — there is no automatic growth. When you add two 4-bit numbers, the result can need five bits (the extra bit is the carry-out). If the output you assign the sum to is only four bits wide, the top bit is dropped and the value truncates. Nothing warns you at run time; the simulation simply shows the low bits.

For example, 4'hF + 4'h2 is 15 + 2 = 17. Seventeen needs five bits (5'b10001). Stored in a 4-bit output, only 0001 (decimal 1) remains. To keep the full result, widen the output — a [4:0] output holds all five bits, carry included. Choosing the right width for every signal is one of the first real hardware-design decisions you make.