Founding beta: Course Orientation and Modules 1–3 are live. Modules 4–7 and the capstone are shipping on the dated schedule below; earnable RTL Proof is targeted for September 5, 2026.

Verilog RTL Foundations

Design real RTL.
Prove it works.

Learn digital logic by writing real Verilog in a browser-based Learning Terminal. Predict, simulate, and preserve evidence you can explain.

See the build path

5-step Orientation + 9-lesson Module 1 · Free after account creation · No payment gate

Prefer to explore first? Try the no-signup RTL Sandbox.

first_gate.v

Mission 01

Make the gate tell the truth.

Predict the output, complete one line of Verilog, then compare your idea with all four input cases.

✓ Prediction recorded

2 · Run the supplied checks

3 · Explain what changed

module and_gate (

input wire a, b,

output wire y

);

assign y = a & b;

endmodule

All 4 checks passed

Run 01

Representative lesson view; product behavior is available to inspect.

Run Verilog in the live RTL Sandbox →

Build

Write synthesizable Verilog in a focused, beginner-safe editor.

Run

Execute real Icarus Verilog simulations and inspect output and waveforms.

Explain

Preserve the reasoning and evidence that turn completion into proof.

Who this is for

A practical first RTL path—not a prerequisite maze.

Built for learners moving toward FPGA, VLSI, semiconductor engineering, RTL design, or verification work who need something concrete to run and explain.

ECE/CE students + recent graduates

Turn digital-logic concepts into simulator-backed Verilog work.

FPGA or VHDL learners

Build a disciplined bridge into synthesizable Verilog RTL.

Hardware-focused CS learners

Prepare for RTL or verification conversations with inspectable evidence.

The Learning Terminal

A lesson is not done until the circuit answers back.

The left pane gives you just enough context. The right pane asks you to predict, build, run, compare, and explain. Heavy tools load only when the task needs them.

01Predict before Run. Make your mental model visible before the simulator gives away the answer.
02Failure becomes feedback. Error Clinics point to the failed behavior and one useful next move.
03Evidence accumulates. Passing checks, waveforms, and explanations feed later project and proof work.

Lesson 3.7 · Counters Predict → Run → Compare

Learn

Watch state change on a clock edge.

A counter stores its current value in a register. At each rising edge, the next value replaces the old one.

Before you run

If the count is 3 now, what should it become after the next rising edge?

Build + Output

✓ checks passed

always @(posedge clk) begin
  count <= count + 1'b1;
end

Example simulation signal values over time
Time	clk	a	b	y
0 ns	0	0	1	0
10 ns	1	1	1	1
20 ns	0	1	0	0

Sample — not a real learner outcome

What RTL Proof is being built to show.

Not a score badge. A learner-controlled work sample that connects source code, passing simulation evidence, waveform evidence, design explanation, and review status.

Honest beta status: this sample illustrates the target artifact. The final capstone and end-to-end earnable RTL Proof are not live yet; the target is September 5, 2026.

RTL Proof · Sample

Tiny Calculator Engine

Example evidence layout · no learner identity

SAMPLE

Simulation

Passing evidence

Directed checks + output log

Waveform

Attached

Key signals and transitions

Review

Target state

Capstone review status

Design explanation

“The controller FSM selects an ALU operation and writes the result into the register file. Separating control from the datapath made each block easier to test…”

Example learner-authored explanation

Skills demonstrated

✓ Controller FSM + datapath integration
✓ Clocked register design
✓ Waveform-based debugging
✓ Verification explanation

Published delivery commitments

Seven modules, plus free onboarding. Every status in the open.

The founding beta is rolling delivery, not a finished-course fiction. Live means usable now. Dated modules are included in Self-Paced when they release.

Start Here

Live now

Course Orientation

See how ideas become circuits and where Verilog fits in the hardware design loop.

Free

Module 1

Live now

Digital Circuits as Verilog

Build gates and multiplexers, run real simulations, and earn the White Belt.

Free

Module 2

Live now

Combinational Building Blocks

Design selectors, decoders, adders, and a mini ALU with latch-free combinational RTL.

Self-Paced

Module 3

Live now

Sequential Design with Verilog

Work with clocks, flip-flops, registers, counters, and the practical meaning of RTL.

Self-Paced

Module 4

Ships Aug 21, 2026

FSMs: Behavior Over Time

Design a sequence-detector controller from state diagram to simulation evidence.

Included at release

Module 5

Ships Aug 28, 2026

Datapath and Control Design

Connect registers, an ALU, buses, and controller signals into a working datapath.

Included at release

Module 6

Ships Aug 31, 2026

Debugging and Verification Awareness

Use test output, waveforms, warnings, corner cases, and timing awareness to find bugs.

Included at release

Module 7

Target: Sep 5, 2026

Capstone: Tiny RTL System

Integrate a controller and datapath into the Tiny Calculator Engine and submit the final evidence package.

Included at release

Scope note: Course 1 uses supplied SystemVerilog checkers but does not teach SystemVerilog testbench authoring, UVM, formal verification, physical design, VHDL, or vendor-specific tool flows.

Self-Paced · Founding beta

$79 USD

one time · no subscription

Founding price: $79 — rises to $149 when Modules 4–7 and the capstone ship (September 2026).

Available now

✓ Everything in the free path
✓ Modules 2–3 with simulator-backed checks
✓ Yellow Belt and Yellow Belt+ recognition

Included as released

✓ Modules 4–7 and capstone
✓ Capstone review
✓ Certificate + RTL Proof eligibility

14-day no-questions refund · 30% off with a verified .edu email

Checkout temporarily unavailable. You can still start free or contact SkillLift Labs for help.

Guided Sprint · Fall cohort

Waitlist only

Structure and expert feedback—after the beta proves the loop.

A manual Fall cohort is planned with a small pod, weekly deadlines, and expert feedback from @silicon-mentor. It is not purchasable now, and dates are not yet set.

Planned price: $149 USD one time. Joining the waitlist is not a purchase or reservation.

Real work

Inspect the mechanism.

Run real Verilog, see exact pass/fail output, inspect waveforms, and use a free no-signup Sandbox before trusting the course.

Clear terms

One payment. Plain dates.

No auto-billing, no fabricated discount timer, no fake learner counts. Rolling delivery and the 14-day refund are stated before checkout.

Learner control

Proof is yours to publish.

Evidence stays tied to your work. Public proof is learner-controlled; a completion claim is never presented as verified work.

Trust + FAQ

The questions worth asking before you pay.

Still unsure where to begin? Take the five-question readiness quiz.

Is this course really free to start?

Yes. Course Orientation and all of Module 1 are free after account creation. No card is requested. The free path includes real simulator-backed exercises and the White Belt checkpoint.

What is available in the paid course today?

Modules 2 and 3 are live now. Modules 4–7, the capstone, capstone review, and RTL Proof eligibility are included in the same one-time purchase as they release on the published schedule above.

Can I earn RTL Proof today?

Not yet. The end-to-end earnable RTL Proof depends on Module 7 and the capstone, targeted for September 5, 2026. Every proof preview on this page is clearly marked as a sample.

Do I need Verilog or digital-design experience?

No. The Orientation and Module 1 ramp starts with digital signals, truth tables, gates, and the shape of a Verilog module. Learners with experience can use the readiness quiz to find a later starting point.

What is outside the scope of Course 1?

This course does not teach SystemVerilog testbench authoring, UVM, formal verification, physical design, VHDL, or vendor-specific tool flows. It introduces timing awareness, but not full static timing analysis.

Who is @silicon-mentor?

Silicon Chip Academy is taught under a pseudonym. We ask you to judge the course by the work you can run and inspect: real simulations, transparent release dates, explicit scope, and a 14-day refund policy.

Your first working circuit is on the free side

Start with Orientation. Decide after the work.

No card, no countdown, and no need to install an FPGA toolchain. Build through the White Belt before choosing whether the paid path is worth it.

Design real RTL.Prove it works.

Make the gate tell the truth.

A practical first RTL path—not a prerequisite maze.

ECE/CE students + recent graduates

FPGA or VHDL learners

Hardware-focused CS learners

A lesson is not done until the circuit answers back.

Watch state change on a clock edge.

What RTL Proof is being built to show.

Tiny Calculator Engine

Seven modules, plus free onboarding. Every status in the open.

Course Orientation

Digital Circuits as Verilog

Combinational Building Blocks

Sequential Design with Verilog

FSMs: Behavior Over Time

Datapath and Control Design

Debugging and Verification Awareness

Capstone: Tiny RTL System

Structure and expert feedback—after the beta proves the loop.

Inspect the mechanism.

One payment. Plain dates.

Proof is yours to publish.

The questions worth asking before you pay.

Start with Orientation. Decide after the work.

Design real RTL.
Prove it works.