Silicon Chip Academy by SkillLift Labs

Founding beta: Course Orientation and Modules 1–3 are live. Modules 4–7 and the capstone are written and included in your purchase, but not released yet — no public date until it is production-verified. Every module's real status is listed below.

Verilog RTL Foundations

Design real RTL.
Prove it works.

Learn digital logic by writing real Verilog in a browser-based Learning Terminal. Predict, simulate, and preserve evidence you can explain.

See the build path

5-step Orientation + 9-lesson Module 1 · Free after account creation · No payment gate

Prefer to explore first? Try the no-signup playground.

first_gate.v

Mission 01

Make the gate tell the truth.

Predict the output, complete one line of Verilog, then compare your idea with all four input cases.

✓ Prediction recorded
2 · Run the supplied checks
3 · Explain what changed

module and_gate (

input wire a, b,

output wire y

);

assign y = a & b;

endmodule

All 4 checks passed

Run 01

Representative lesson view; product behavior is available to inspect.

Run Verilog in the live playground →

Build

Write synthesizable Verilog in a focused, beginner-safe editor.

Run

Execute real Icarus Verilog simulations and inspect output and waveforms.

Explain

Preserve the reasoning and evidence that turn completion into proof.

Who this is for

A practical first RTL path—not a prerequisite maze.

Built for learners moving toward FPGA, VLSI, semiconductor engineering, RTL design, or verification work who need something concrete to run and explain.

ECE/CE students + recent graduates

Turn digital-logic concepts into simulator-backed Verilog work.

FPGA or VHDL learners

Build a disciplined bridge into synthesizable Verilog RTL.

Hardware-focused CS learners

Prepare for RTL or verification conversations with inspectable evidence.

The Learning Terminal

A lesson is not done until the circuit answers back.

The Lesson gives you just enough context. Your Task asks you to predict, build, run, compare, and explain. Heavy tools load only when the task needs them.

  • 01Predict before Run. Make your mental model visible before the simulator gives away the answer.
  • 02Failure becomes feedback. Error Clinics point to the failed behavior and one useful next move.
  • 03Evidence accumulates. Passing checks, waveforms, and explanations feed later project and proof work.
Lesson 3.7 · Counters Predict → Run → Compare

Learn

Watch state change on a clock edge.

A counter stores its current value in a register. At each rising edge, the next value replaces the old one.

Before you run

If the count is 3 now, what should it become after the next rising edge?

Build + Output

✓ checks passed
always @(posedge clk) begin
  count <= count + 1'b1;
end
Skip example signal table
Example simulation signal values over time
Timeclkaby
0 ns0010
10 ns1111
20 ns0100
End of example signal table
Sample — not a real learner outcome

What an earned RTL Proof can show.

Not a score badge. A learner-controlled work sample that connects source code, passing simulation evidence, waveform evidence, design explanation, and review status.

Honest beta status: this is an illustrative sample, not a learner's credential. The earnable path is no public date until it is production-verified.

RTL Proof · Sample

Tiny Calculator Engine

Example evidence layout · no learner identity

SAMPLE

Simulation

Passing evidence

Directed checks + output log

Waveform

Attached

Key signals and transitions

Review

Target state

Capstone review status

Design explanation

“The controller FSM selects an ALU operation and writes the result into the register file. Separating control from the datapath made each block easier to test…”

Example learner-authored explanation

Skills demonstrated

  • ✓ Controller FSM + datapath integration
  • ✓ Clocked register design
  • ✓ Waveform-based debugging
  • ✓ Verification explanation

Module-by-module status

Seven modules, plus free onboarding. Every status in the open.

The founding beta is rolling delivery, not a finished-course fiction. Live means usable now. Pending means written but not yet released — included in the Interactive Course at no extra charge the moment it goes live.

Start Here

Live now

Course Orientation

See how ideas become circuits and where Verilog fits in the hardware design loop.

Free

Module 1

Live now

Introduction to Logic Circuits and Verilog

Build gates and multiplexers, run real simulations, and earn the White Belt.

Free

Module 2

Live now

Combinational Building Blocks

Design selectors, decoders, adders, and a mini ALU with latch-free combinational RTL.

Interactive Course

Module 3

Live now

Sequential Design with Verilog

Work with clocks, flip-flops, registers, counters, and the practical meaning of RTL.

Interactive Course

Module 4

Built — pending production release

FSMs: Behavior Over Time

Design a sequence-detector controller from state diagram to simulation evidence.

Included at release

Module 5

Built — pending production release

Datapath and Control Design

Connect registers, an ALU, buses, and controller signals into a working datapath.

Included at release

Module 6

Built — pending production release

Debugging and Verification Awareness

Use test output, waveforms, warnings, corner cases, and timing awareness to find bugs.

Included at release

Module 7

Built — pending production release

Capstone: Tiny RTL System

Integrate a controller and datapath into the Tiny Calculator Engine and submit the final evidence package.

Included at release

Scope note: Course 1 uses supplied SystemVerilog checkers but does not teach SystemVerilog testbench authoring, UVM, formal verification, physical design, VHDL, or vendor-specific tool flows.

Interactive Course · Founding beta

$79 USD

one time · no subscription

Learn on your schedule with real simulation, instant checks, waveforms, project slices, capstone review, and RTL Proof eligibility.

Founding beta price: $79 USD one time. Founding learners keep complete Interactive Course access at this price.

Everyone who buys at the founding price keeps complete Interactive Course access at that price — we never charge the difference later.

Available now

  • ✓ Everything in the free path
  • ✓ Modules 2 and 3 available now, simulator-backed end to end
  • ✓ Simulator-backed lessons with hidden checks, waveforms, and honest pass/fail
  • ✓ Yellow Belt and Yellow Belt+ recognition on your profile

Included as released

  • ✓ Modules 4–7 and capstone
  • ✓ Capstone review
  • ✓ Certificate + RTL Proof eligibility

14-day no-questions refund · 30% off with a verified .edu email

Checkout temporarily unavailable. You can still start free or contact SkillLift Labs for help.

Guided Sprint · Waitlist

Waitlist only

Structure and expert feedback—after the beta proves the loop.

A manually run cohort is planned with a small pod, weekly deadlines, and expert feedback from @silicon-mentor. It is not purchasable, and its dates are not set.

No price yet: we will not name one until founding beta shows what live sessions, mentor feedback, and capstone review actually cost to run. Joining the waitlist is not a purchase or reservation.

Real work

Inspect the mechanism.

Run real Verilog, see exact pass/fail output, inspect waveforms, and use a free no-signup playground before trusting the course.

Clear terms

One payment. Plain dates.

No auto-billing, no fabricated discount timer, no fake learner counts. Rolling delivery and the 14-day refund are stated before checkout.

Learner control

Proof is yours to publish.

Evidence stays tied to your work. Public proof is learner-controlled; a completion claim is never presented as verified work.

Trust + FAQ

The questions worth asking before you pay.

Still unsure where to begin? Take the five-question readiness quiz.

Is this course really free to start?

Yes. Course Orientation and all of Module 1 are free after account creation. No card is requested. The free path includes real simulator-backed exercises and the White Belt checkpoint.

What is available in the paid course today?

Modules 2 and 3 are live now. Modules 4–7, the capstone, capstone review, and RTL Proof eligibility are written and included in the same one-time purchase, and unlock for you the moment each one is released — at no extra charge. The status of every module is shown above.

Can I earn RTL Proof today?

Not yet. The end-to-end earnable RTL Proof depends on Module 7 and the capstone, which are written but not yet released — no public date until it is production-verified. Every proof preview on this page is clearly marked as a sample.

Do I need Verilog or digital-design experience?

No. The Orientation and Module 1 ramp starts with digital signals, truth tables, gates, and the shape of a Verilog module. Learners with experience can use the readiness quiz to find a later starting point.

What is outside the scope of Course 1?

This course does not teach SystemVerilog testbench authoring, UVM, formal verification, physical design, VHDL, or vendor-specific tool flows. It introduces timing awareness, but not full static timing analysis.

Who is @silicon-mentor?

Silicon Chip Academy is taught under a pseudonym. We ask you to judge the course by the work you can run and inspect: real simulations, transparent release dates, explicit scope, and a 14-day refund policy.

Your first working circuit is on the free side

Start with Orientation. Decide after the work.

No card, no countdown, and no need to install an FPGA toolchain. Build through the White Belt before choosing whether the paid path is worth it.