Module 3 Checkpoint Review

Module 3 moves from circuits that react immediately to circuits that remember. A clocked block captures values on an edge, and registers hold those values between edges. Synchronous reset gives stored state a known value on a clock edge.

Use non-blocking assignments for clocked register updates. They preserve before-and-after behavior when several registers update on the same edge. This is what lets a multi-stage pipeline delay data by one edge per stage.

Counters calculate a next value from the current count and wrap when the result exceeds their width. Shift registers move stored bits one position per edge while accepting or producing a serial stream. Both are repeated applications of the same register-update pattern.

The module’s formal definition ties these ideas together: RTL describes registers, combinational logic between them, and data movement from register to register on clock edges. A signal timeline provides the evidence for when values are captured, held, shifted, incremented, or reset.