4-to-1 MUX

A 4-to-1 MUX scales the idea of selection: it has four data inputs and a 2-bit select, and the select value chooses which input reaches the output. Two select bits encode four cases — 00, 01, 10, 11 — one per data input.

The behavior is again a routing table: each select pattern names exactly one input to pass through. Writing that table out first, in counting order, removes any ambiguity about which input each select value chooses.

In Verilog the same conditional-operator idea extends to four cases, and the underlying hardware is still pure routing — no arithmetic, no memory, just the select value steering one of four inputs to the output.