FSMs as Stories

A finite state machine (FSM) is a way of describing a system that behaves differently depending on what has already happened, not just what its inputs are right now. Before any diagram or line of Verilog, three plain ideas cover everything an FSM needs.

A state is where the system currently stands — one condition out of a fixed set of possibilities. A vending machine tracking how much money it has received is in one of a few states: it has received $0, $0.25, $0.50, or $0.75 so far. A traffic light is in one of a few states too: which direction currently shows green, and which shows yellow.

A transition is the event that moves the system from one state to another. For the vending machine, inserting a coin is a transition — it moves the machine from "received $0.50" to "received $0.75." For the traffic light, a timer reaching its set duration is the transition that moves the light from NS-green to NS-yellow.

The output is what the system does while it is in a state (or, for some designs, as it makes a particular transition). The vending machine's output while in its final state is to release the item and any change. The traffic light's output while in NS-green is exactly that: NS shows green, EW shows red.

Every FSM you build in this module — a sequence detector, a traffic light, a vending machine — is described with exactly these three pieces. The rest of Module 4 gives you a picture for it (the state diagram), then a way to write it in Verilog (the state register and next-state logic), then a way to make its outputs behave the way you intend (Moore vs Mealy timing).