Moore vs Mealy Output Timing

An FSM's output logic can be written in one of two styles, and the difference is entirely about what the output depends on.

Moore-style output depends only on the current state:

assign z = (state == S3);

Because it reads nothing but state, and state itself only changes on a clock edge, a Moore-style output is stable for the entire duration of a state. It cannot change mid-state no matter what the input does — it can only change right after the state register updates.

Mealy-style output depends on the current state and the current input:

assign z = (state == S2) && w;

Because this reads w directly, it can change the instant w changes — even in the middle of a state, well before the next clock edge. If w glitches or wiggles between edges, a Mealy-style output can glitch right along with it.

Course 1 uses Moore-style output as the default for exactly this reason: stable, edge-aligned outputs are easier to reason about and easier to hook up to other clocked logic without worrying about mid-cycle glitches. Mealy-style output is real and sometimes genuinely useful — it can save a clock cycle of latency in some designs, since the output can react before the state itself has caught up — but that timing benefit comes with the cost of a less predictable signal. This course shows Mealy only as a contrast, not as something you will be asked to design with at launch.

When you are deciding which style to reach for on your own designs later, ask one question: does this output need to be stable and edge-aligned, or does it need to react immediately to the input? Moore covers the first case; Mealy covers the second.