Why Circuits Need Memory

Every circuit you built in Module 2 was combinational: its output depended only on the inputs present right now. Change an input and the output reacts immediately, with nothing held over from before. A multiplexer, a decoder, and an adder are all combinational — they have no sense of the past.

Sequential circuits are different: their output depends on history, not only on the current inputs. A circuit that reports "the value the input had one clock edge ago" or "keep this value until a control signal clears it" has to store something. That storage is memory, and the clock is what decides the exact moment a circuit captures its next value.

You can usually spot memory in plain English. Phrases like "one cycle ago", "keeps its value", or "holds until cleared" look backward in time, so they need memory. Phrases like "right now" or "the combination of its inputs" describe combinational behavior with no memory.

In Verilog, the signal is the block header. assign and always @(*) both describe combinational logic that tracks its inputs continuously. A clocked block written always @(posedge clk) is the clearest sign a design holds state: it captures a value on the rising edge and keeps it until the next one. The rest of Module 3 is about writing that kind of block correctly.