More Gates: OR, NOT, XOR
Reference for the Verilog OR (|), NOT (~), and XOR (^) operators and the truth-table pattern each one produces.
Updated 2026-06-05
Once AND makes sense, three more operators cover most combinational logic. OR (|) outputs 1 when at least one input is 1. NOT (~) inverts a single input. XOR (^) outputs 1 when its two inputs differ.
Each operator corresponds to exactly one truth-table pattern, so choosing a gate is really choosing the table you want. Swapping one operator for another changes the behavior while leaving the module skeleton — ports, body shape, endmodule — untouched.
A common trap is mixing bitwise and logical operators: | is bitwise OR, || is logical OR, and they are not interchangeable for gate-level work. When an output looks wrong, confirm the operator matches the truth table you meant to build.