Combinational RTL
Basic Encoder
How a one-hot-to-binary encoder works in Verilog, and why it assumes only one input is active at a time.
1 min read · Updated
An encoder is the reverse of a decoder: a one-hot input (exactly one active line among several) maps to a compact binary output. A 4-to-2 encoder takes a 4-bit one-hot input and produces a 2-bit binary output identifying which line was active.
A basic encoder assumes exactly one input is active at a time. Two kinds of input break that assumption and only one of them is obvious: more than one line active, and no line active at all. Neither pattern matches any of the case items the encoder lists, so in both cases the output falls back on whatever default was assigned at the top of the block — not a crash, but not a meaningful answer either. An all-zero input is the easier one to forget, because nothing about it looks like a conflict.
Priority encoders exist specifically to resolve this ambiguity: they define a priority order among the inputs, so a well-defined output is produced even when multiple inputs are active at once. A basic encoder should only be used where the one-active-input assumption genuinely holds.