Counters in Verilog

A counter is a register whose next value is calculated from its current value. On each enabled rising edge, it loads the current count plus one. Between edges it holds steady, just like any other register.

The width determines the range. A 4-bit counter represents 0 through 15. Adding one to 15 produces a carry that does not fit in four bits, so the stored four-bit result becomes 0. This rollover is called wrap behavior.

Reset and enable give the counter useful control. A synchronous reset loads a known starting value on an edge. An enable decides whether the edge increments the count or leaves it unchanged. Check reset first, then enable, so reset has clear priority.

When reading a counter waveform, decide what “cycle 0” means before counting edges. If cycle 0 is the reset value, cycle 1 is the value after the first enabled edge. Marking this convention avoids most off-by-one mistakes.