Debug and Fix Project Slice

A repeatable workflow for locating the first divergence, fixing a planted RTL bug, and recording root cause.

Updated 2026-07-26

This project slice asks you to repair one rotating faulty implementation of an overlapping sequence detector. The checker is deterministic, but the planted bug may be in combinational next-state logic, sequential update ordering, or a missing state behavior.

Use a narrow debugging loop:

  1. Predict the first input cycle where observed behavior should diverge from the specification.
  2. Run the checker and read the earliest failing observation.
  3. Trace that observation backward through the output and state-update logic.
  4. Make the smallest change that restores the intended hardware behavior.
  5. Rerun the full checker, including reset, overlap, and no-match cases.

After the checker passes, write the root cause in terms of hardware behavior. Name the faulty structure, explain why it produced the divergence, and state why the fix covers more than the first failing case.

Avoid documenting only the edited line. A useful engineering note should help another person recognize the same bug class in different RTL.