Module 4 Checkpoint Review

Module 4 builds finite state machines from the same story-first approach the rest of this course uses: identify states, transitions, and outputs before writing any Verilog, then build from a state diagram to a state table to working code.

The dual-block FSM pattern splits every design into two jobs. A clocked state register stores the current state and never decides anything — it only samples whatever the next-state logic computed, on the clock edge. Combinational next-state logic decides what the next state should be and never stores anything itself. Keeping those two jobs in separate blocks makes each one easier to read and to debug in isolation.

Two different safety nets guard against different problems in next-state logic. A default assignment at the top of the block covers any input a case item's condition does not explicitly handle, so the design holds its current state instead of leaving a signal undriven. A separate default: case item covers a state code that no case item lists at all — without one, reaching an unused code would leave the design stuck there forever, with no path back to a known state.

Output timing is a real design choice, not just vocabulary. A Moore-style output depends only on the current state, so it stays stable for an entire state's duration — the safer default for most control logic. A Mealy-style output depends on state and the current input together, so it can react the instant an input changes, without waiting for the next clock edge. A detector that needs to flag a match the moment it completes is exactly the kind of case where that one-cycle-earlier reaction is worth the tradeoff.

The module's project slice works the same way every project slice in this course will: pass the hidden deterministic checks, document a state table, and explain a real design decision in fifty to one hundred words. Passing code by itself is not a complete submission.