Building the Capstone Datapath

A concept-level guide to wiring the supplied register file and ALU into the capstone datapath.

Updated 2026-07-27

tiny_calc_datapath wires two already-complete blocks together: reg_file_4x4 (built the same way as Lesson 5.5/5.9) and alu_4bit (built the same way as Lesson 2.13, now with SUB added).

Three connections make the wiring work:

  1. The ALU's result output reaches the register file's wdata write-data port — so a completed computation can be stored back.
  2. The register file's first read port (rs1_data) reaches the ALU's a input.
  3. The already-supplied immediate MUX (alu_b) reaches the ALU's b input, choosing between the second register read and an immediate value.

The supplied testbench acts as a controller stub: it drives reg_write_en, waddr, and alu_op directly, the same way a real controller eventually will in Lesson 7.5. That lets you prove the datapath's wiring in isolation, before the real FSM exists.

A register file with no other bootstrap path starts every register at an unknown value after power-on. The controller-stub testbench resets first, then writes each seed value through the ALU's own ADD-with-immediate path (0 + value) — a pattern worth remembering any time a testbench needs a known starting state without a dedicated load port.