Common Sequential Bugs

Most sequential mistakes fall into one of four classes.

Missing reset. Stored state begins as X — unknown — because no path assigns it a known value before the design starts relying on it. It resolves to a real value only once real data first passes through, which can be many cycles into the simulation.

Wrong assignment type. Mixing blocking (=) and non-blocking (<=) assignments inside a clocked block can collapse a delay that should span two clock edges into a single edge, because a blocking assignment's right-hand side can see a value that was only just updated in the same block, rather than the value that existed before the edge.

Wrong clock edge. The sensitivity list names negedge where the design (and the testbench that checks it) expects posedge, or the reverse. Every captured value still updates once per cycle, but consistently half a cycle away from when it should.

Enable bug. A register's enable signal never actually asserts, so the register keeps sampling its input but the assignment that would let it load never has permission to run — the register holds its reset value no matter what the testbench drives.

The waveform clue differs for each: missing reset shows X persisting longer than expected; wrong assignment type shows two stages changing together instead of one edge apart; wrong clock edge shows a value updating at a consistent offset from the edge you expected; enable bug shows a value that never changes from its reset value at all, even while inputs are actively changing around it. None of these clues is a guarantee — real bugs occasionally produce a mixed or unusual pattern — but matching the observed behavior to the closest class turns a vague "it is wrong" into a first hypothesis worth testing, which you then confirm by inspecting the RTL and rerunning.