Debugging, Timing, and Synthesis
Common Sequential Bugs
The four bug classes behind most sequential mistakes — missing reset, wrong assignment type, wrong clock edge, and enable bug — and how each shows up in a waveform.
2 min read · Updated
Four common classes of sequential mistake are worth knowing on sight.
Missing reset. Stored state begins as X — unknown — because no path assigns it a known value before the design starts relying on it. It resolves to a real value only once real data first passes through, which can be many cycles into the simulation.
Wrong assignment type. A blocking assignment (=) in a clocked block updates its register at once, so a later line in the same block reads the new value rather than the value from before the edge. In a two-stage chain, the second stage should stay one rising edge behind the first; with a blocking first stage, both stages change on the same edge (Lesson 3.9). Use non-blocking <= for registers in clocked blocks.
Wrong clock edge. The sensitivity list names negedge where the design (and the testbench that checks it) expects posedge, or the reverse. The register still updates once per cycle, but every change lands on the opposite edge of the clock from the one the specification uses. A check made just after a rising edge can still read a plausible value; a check made just after a falling edge exposes the fault.
Enable bug. The condition that lets a register load is wrong. If it never becomes true, the register holds its reset value no matter what the testbench drives; if it is true when it should be false, the register loads values it should have ignored.
The waveform clue differs for each: missing reset shows X persisting longer than expected; wrong assignment type shows two stages changing together instead of one edge apart; wrong clock edge shows a value updating at a consistent offset from the edge you expected; enable bug shows a value that holds when it should load, or loads when it should hold. None of these clues is a guarantee — real bugs occasionally produce a mixed or unusual pattern — but matching the observed behavior to the closest class turns a vague "it is wrong" into a first hypothesis worth testing, which you then confirm by inspecting the RTL and rerunning.