Control Signals
How small control wires coordinate register writes, MUX paths, and ALU operations in an RTL datapath.
Updated 2026-07-21
Control signals are the small wires that coordinate the datapath. A write-enable signal decides whether a register loads on an active clock edge. A MUX select chooses a data route. An ALU operation code chooses the transformation to apply.
Controllers commonly set several control signals together for one named operation. A table is a useful way to record those choices because it lets you compare operations and see exactly which route or computation changes.
Defaults matter in combinational control logic. Start each output at a safe inactive value, then override only the signals required by a listed operation. That makes unspecified cases predictable and prevents accidental retained behavior.