Digital Logic Foundations
More Gates: NAND, NOR, XNOR
Reference for the NAND, NOR, and XNOR gates and how to write each one in Verilog by inverting its AND, OR, or XOR partner with ~( ).
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Three more gates are the inverted forms of gates you already know. NAND is AND followed by NOT, NOR is OR followed by NOT, and XNOR is XOR followed by NOT. Each one outputs the opposite of its partner on every row of the truth table.
Verilog has no separate single-character operator for NAND or NOR, so you build each one from its partner: write the partner's expression, wrap it in parentheses, and put ~ in front. For example, ~(a & b) inverts AND, so it is NAND. The parentheses make the whole gate result the input to NOT. NOR and XNOR follow the same two steps with their own partner operator. For two inputs, a ~^ b is another spelling of the inverted XOR expression.
The parentheses decide what ~ inverts. ~(a & b) inverts the whole AND result. ~a & b inverts only a first, then ANDs it with b, which is a different circuit. When an output looks wrong, check where the parentheses sit.