Building with Submodules

Large designs are not written as one giant module. You build small, well-tested modules and connect them together by instantiating them. An instantiation names an internal copy of a module and wires its ports to signals in the parent.

Prefer named port mapping — .a(in_a) — over ordered mapping, where you rely on the position of each connection. Named mapping is explicit and survives a port being added or reordered later; ordered mapping silently connects the wrong signals when the port list changes. As the port count grows, named mapping is the safer default.

Hierarchy is a construct for humans reading the source, not a layer that survives into hardware. When a design is flattened, the submodule boxes disappear and every gate ends up in one flat circuit. This is why a two-level source design and its flattened form behave identically: the hierarchy organized your code, not the silicon.