Registers with Enable

A register is a row of flip-flops that all share the same clock. Where a single D flip-flop stores one bit, a register stores several bits side by side. The width comes straight from the vector declaration: output reg [3:0] value is four parallel flip-flops, all loading or holding together on the same edge.

An enable signal lets you control when the register loads. Without an enable, a register captures its input on every clock edge. With an enable, it loads new data only when the enable is high and otherwise holds whatever it already had:

always @(posedge clk) begin
  if (rst)     value <= 4'b0000;
  else if (en) value <= din;
end

The order matters. On each rising edge the block checks reset first, then enable. When reset is high it loads a known 0. When enable is high it loads din. When both are low, neither branch runs — and because this is a clocked block, an unassigned register simply keeps its previous value. That "do nothing" case is exactly the hold behavior you want.

Enables show up everywhere in real designs: pausing a counter, latching a result only when it is valid, or loading a configuration value once and holding it. The pattern is always the same — a clocked block, a reset for known startup, and an enable that decides whether this edge loads or holds.