Common Combinational Bugs

Most combinational mistakes fall into one of four classes.

Wrong operator. Using & where the design needs |, or the reverse. The result looks almost right — it matches the correct behavior for some inputs and flips for others, specifically the inputs where the two operators disagree.

Missing default. An output is left unassigned on some path inside always @(*), so the synthesizer infers a latch to hold the old value. This is the same accidental-latch trap covered in Module 2; the fix is the same default-at-top pattern.

Wrong case item. A case item is mistyped, or a value is accidentally listed twice. Verilog's case statement matches the first item whose value equals the selector and stops looking — so a duplicated value means the second occurrence never runs, and the value it should have matched falls through to whatever the default (or nothing) provides instead.

Width mistake. An expression is evaluated at a narrower width than its destination. Widening happens too late to matter if only the destination is declared wider; the arithmetic itself needs the wider width, for example by zero-extending an operand before an addition whose carry bit matters.

Each class tends to show up differently in a failing testbench: wrong operator flips specific inputs, missing default holds a stale value instead of updating, wrong case item drops one specific input pattern entirely, and width mistake silently truncates a result that is otherwise structurally correct. Reading which inputs fail — and which pass — before opening the RTL usually narrows the search to a first hypothesis among these four. Treat that hypothesis as a starting point: the RTL and a rerun are what actually confirm it.