Building a Tiny Datapath from Supplied Blocks

Integration is the work of making module interfaces agree. When a register file and ALU are already correct, the top-level task is to connect their ports so one readable data route implements the spec.

Start by naming intermediate values. A register-file read can become rs1_data; a MUX-selected second operand can become alu_b; the transform can become alu_result. These names turn a large port map into a route you can read from left to right.

Then identify the control decisions. A select signal chooses whether alu_b comes from another register or an immediate value. An operation signal tells the ALU which transform to perform. A write-enable signal decides whether a destination stores the result on a clock edge.

Check integration in small cases:

1. prove the register-to-register route;
2. change only the MUX selection and prove the immediate route;
3. change only the ALU operation and prove a second transform;
4. disable writing and prove stored data remains unchanged.

This isolates one connection or decision at a time. If a check fails, trace the named route before changing a supplied submodule.