Verilog Module Structure

Reference for the parts that form every Verilog module: the module keyword, the port list, the body, and endmodule.

Updated 2026-06-05

Every Verilog design is a module — a named block with a defined boundary. Four structural parts appear in every one: the module keyword and name, the port list that declares input and output signals, the body that describes behavior, and the closing endmodule.

The port list is the module's contract with the outside world: it names what comes in and what goes out, and nothing else crosses the boundary. The body then describes how the outputs depend on the inputs, using continuous assignments or procedural blocks.

Reading an unfamiliar module is easiest in this order: find the name, read the ports to learn its interface, then read the body to learn its behavior. The lessons keep this skeleton constant so you can focus on the body.