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Silicon Chip Academy Verilog Tutorial

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Where Verilog Fits in the Toolchain

A short reference for how Verilog hardware descriptions move through simulators, waveforms, and synthesis on the way to a working circuit.

2 min read · Updated

Verilog is a hardware description language: you use it to describe what a circuit is, not to write a program that runs line by line. A simulator reads your Verilog plus a supplied checker and shows the resulting behavior — often as a waveform over time — so you can check it against what you intended.

Two tools sit on either side of your description. A simulator answers "does this behave correctly?" by exercising the design with test inputs. A synthesizer answers "can this be built?" by translating a restricted, synthesizable subset of Verilog into a network of real gates.

This course stays inside that synthesizable subset and leans on simulation to prove behavior. Knowing which tool you are talking to — simulator or synthesizer — explains why some Verilog is fine for a quick test but not for hardware.

The six stages, in plain English

Orientation 3 asks you to put these in the order your work passes through them. Each one is defined here so the names are never doing unexplained work:

  • Verilog design — the circuit description an engineer writes by hand. This is the artifact you author in almost every lesson.
  • Supplied checker — a separate file that feeds test values into a design and states what it expects back. This course supplies the checker for you until you learn to read one yourself.
  • Simulator — a program that runs a design and its supplied checker together and reports what happened.
  • Waveform — a picture of how signals changed during a simulator run, drawn as a value per signal along a time axis.
  • Synthesis — turning a checked design into a network of real gates, which is the step that decides whether the description is buildable at all.
  • Hardware — the physical chip or programmable board those gates are finally built into.

Two of these names get used loosely elsewhere. "Simulation" sometimes means the whole run, design plus supplied checker; "synthesis" sometimes means the whole path from description to a placed circuit. When a lesson needs the narrower meaning, it says so.