Buses, Widths, and Bit Slices

A practical guide to multi-bit signals, explicit bit slices, and avoiding accidental width mismatches in Verilog.

Updated 2026-07-21

A bus is a group of bit wires named together. In Verilog, wire [3:0] data describes a four-bit bus. The left index is the most-significant bit and the right index is the least-significant bit in this conventional declaration.

A slice selects a range from a bus. For example, data[7:4] selects four upper bits from an eight-bit value, while data[3:0] selects its lower four bits. Count both endpoints when checking a width.

Make width conversions intentional. If a smaller value goes onto a wider bus, state how it is extended. If a wider value goes into a smaller destination, state which bits are retained. Explicit choices are easier to review and less likely to hide a design mistake.