The State Register

The state register is the piece of an FSM that actually holds its current state between clock edges. It is a clocked register — built exactly like the synchronous-reset D flip-flops from Module 3, just widened to a multi-bit state value instead of a single bit.

always @(posedge clk) begin
  if (reset) cur_state <= IDLE;         // known startup state
  else       cur_state <= next_value;   // otherwise, sample what next-state logic computed
end

On the rising edge, the state register checks reset first: if the reset input is high, it loads a known startup state so the circuit always starts from a known condition instead of an arbitrary one. Otherwise, it samples the computed next-state value — a value that some other, purely combinational block worked out for it.

This is the defining feature of the dual-block FSM pattern this course uses: the state register never decides anything. It only stores whatever the next-state signal says, on the clock edge, and holds that value until the next edge. Deciding what that next-state value should be is a completely separate job, done by combinational next-state logic — a block that reacts instantly to the current state and the current input, but never stores anything itself.

Splitting storage and decision-making into two blocks like this is not just a style preference. It keeps each block's job legible: if a design behaves incorrectly, you can ask "is this a storage problem or a decision problem?" and know exactly which block to inspect.