Module 2 Checkpoint — Further Reading

The Module 2 Checkpoint confirms that you can build combinational hardware in Verilog, avoid the most common latch-inference mistake, and read a simple testbench — the same skills you practised in Lessons 2.1 through 2.14.

What you demonstrated:

• Writing procedural combinational logic with always @(*), if/else, and case, always assigning every output on every path.
• Building selectors, decoders, encoders, adders, and a mini ALU from those constructs.
• Reasoning about vector widths and recognizing truncation when a result does not fit.
• Reading a supplied SystemVerilog testbench and tracing a failing check back to its input pattern.

If any recall question felt shaky, revisit the lesson it draws from:

Recall question	Skill	Source lesson
The latch trap	Default-assignment-at-top discipline	Lesson 2.12
The case default	Guaranteeing every output path is assigned	Lesson 2.4
The width mismatch	Vector width and truncation	Lesson 2.8

Up next: Module 3 introduces sequential logic — flip-flops, registers, counters, and shift registers, all driven by a clock. Everything you built in Module 2 stays combinational; Module 3 is where circuits start to remember.