case Statements

How case describes multi-way selection in Verilog, and why a default branch matters even when every value seems already listed.

Updated 2026-07-07

case is the clearer way to describe multi-way selection once there are more than two choices. Each case item maps one select value to one output assignment; the order the items appear in does not change the resulting hardware, unlike an if/else if chain where order can matter.

A default branch (or a default-assignment-at-top) is still required, even in a case statement. case only guarantees correct output for the values you explicitly wrote — any select value you did not list falls through unassigned, and the synthesizer infers a latch to hold the previous output.

This matters even when a selector's width means every value is technically covered today: a default is a defensive habit that protects the design if the selector ever grows, or if a value was simply missed during a busy afternoon of coding.