Combinational RTL
case Statements
How case describes multi-way selection in Verilog, and why a default branch matters even when every value seems already listed.
2 min read · Updated
case is the clearer way to describe multi-way selection once there are more than two choices. Each case item maps one select value to one output assignment; the order the items appear in does not change the resulting hardware, unlike an if/else if chain where order can matter.
Two different things are called "default" here, and they do different jobs. Keep them apart.
The assignment at the top of the block is what makes assignment complete. If it is there, every route through the block has already given the output a value before case is reached, so no unmatched value can leave it unassigned and no latch is inferred.
The default: item inside the case decides what unmatched values should produce. Remove it from a block that still assigns at the top and nothing becomes a latch — those values simply fall back on the top assignment, which silently changes the function rather than the circuit's combinational nature.
The latch appears only when neither is present: no matching item, no default:, and no earlier assignment. Then the description really does ask for the previous value to be held, and storage is what holds it. Write both, for the two separate reasons.
This matters even when a selector's width means every value is technically covered today: a default is a defensive habit that protects the design if the selector ever grows, or if a value was simply missed during a busy afternoon of coding.