Debugging Sequential Verilog

Sequential bugs are easiest to diagnose when you compare the signal timeline with the clock. First find the edge where the observed value diverges from the expected value. Then ask which rule could produce that timing symptom.

Four beginner bug classes cover many failures:

• Wrong assignment type: stages that should be one edge apart change together because a clocked data path uses blocking assignments.
• Missing reset: a stored value begins as X, meaning unknown, and remains unusable until some later assignment gives it a known value.
• Wrong edge: the output changes on falling edges when the specification expects rising edges, or the reverse.
• Width mismatch: upper bits disappear because a result is stored in a register that is too narrow.

Inspect one class at a time. For timing that is too early, check assignment operators and the sensitivity list. For an unknown startup value, check reset behavior. For a numerically truncated value, compare every expression width with the destination register width.

After a fix, rerun the smallest stimulus that exposed the problem and read the timeline again. A clean compile is not enough; the value must change on the intended edge and hold correctly between edges.