Clean Hardware Structure

Lint is an automated style-and-structure check for HDL. Simulation asks whether a chosen set of inputs produced expected outputs; lint asks whether the description contains suspicious structures even when a test happens to pass.

An unused signal is declared or computed but never consumed. It may be harmless cleanup, or it may reveal that a result was supposed to reach another block but was never connected.

An undriven output has no source. A port can exist in a module interface while no continuous assignment, procedural assignment, or submodule output supplies its value.

A width mismatch connects values with different bit counts. Sometimes extension or truncation is deliberate, but it should be visible in the code.

Arithmetic is the case worth memorising, because the rule is not the intuitive one: in a continuous assignment Verilog sizes the expression from its assignment context, not from its operands. So

wire [4:0] total;
assign total = a + b;   // a, b are 4-bit — the add is evaluated at 5 bits, carry preserved

is already correct. The carry is lost only when the sum passes through something narrower on the way:

wire [3:0] sum = a + b; // the add is evaluated at 4 bits here — carry discarded
assign total = sum;     // zero-extending afterwards cannot recover it

Widening the final destination alone never helps; the fix belongs wherever the addition is actually assigned. Give it a wide enough destination (wire [4:0] sum = a + b;), zero-extend the operands ({1'b0, a} + {1'b0, b}), or drop the narrow intermediate entirely.

A combinational loop feeds a combinational result back into itself without clocked storage to separate one update from the next. That structure has no simple “previous cycle” value and usually signals a design error.

Treat warnings as questions to answer, not messages to silence. Identify the class, trace the affected route, and make the intended width or driver explicit.