AI and Verilog Verification

AI-generated Verilog is an untrusted draft. Clear formatting and a passing test do not prove that the described hardware is complete.

Use three independent review lenses:

1. Read the RTL. List the intended inputs, outputs, branches, defaults, and state updates.
2. Run selected behavior checks. Include normal cases, boundaries, disabled modes, and any input combination the draft handles implicitly.
3. Read static warnings. An inferred latch, width mismatch, undriven signal, or combinational loop can expose a structural risk that selected simulation cases never activated.

Passing selected tests means only that those tests did not reveal a mismatch. It does not cover omitted cases, incorrect assumptions in the prompt, or suspicious hardware inferred outside the checked outputs.

When a warning appears after a passing run, do not choose which result to “believe.” They answer different questions. Preserve both pieces of evidence, identify the untested path or signal, and expand the review.

The engineer remains accountable for the specification, the test set, the warning triage, and the final RTL.