Submitting the Tiny Calculator Engine RTL Proof

A field-by-field guide to the final capstone bundle, expert review, and private-to-public proof flow.

Updated 2026-07-28

The final bundle has four layers:

  1. Verified RTL: the server resolves current passing attempts for the ALU, register file, controller, and integrated top. A prose claim cannot replace a missing passing check.
  2. Design reasoning: explain architecture, the datapath/control boundary, clocked write timing, and one tradeoff in 200–400 words.
  3. Verification and debug evidence: explain coverage in 100–200 words, classify warnings, document one bug, and include before/fixed observations plus a real labelled waveform.
  4. Self-review: preserve all eight checked or unchecked selections. Reviewers need the honest snapshot.

The private draft autosaves. Submission creates an immutable revision and enters expert review for both launch tiers under the stated business-day service level. While review is pending, the employer preview is read-only and sharing remains disabled.

After approval, the existing certificate pipeline issues the Verilog RTL Foundations Certificate and RTL Proof. You control whether the proof is private or public; a public proof is available at /verify/{credentialId} and only then is the share action enabled.