Combining Gates with Internal Signals

Reference for wire declarations in Verilog: naming an intermediate signal so one gate output can feed another gate input.

Updated 2026-06-05

Real circuits chain gates together, and the connection between them needs a name. A wire declaration creates an internal signal: a value that is not an input or an output, but a private connection inside the module.

The pattern is always the same. One assignment drives the wire — the wire is on the left — and a later assignment consumes it, where the wire appears on the right. Tracing a signal means finding the line that drives it and the line that uses it: the producer and the consumer.

This driver-and-consumer idea scales. A multi-gate circuit is just several internal wires, each driven once and read where needed. Naming intermediate signals clearly is what keeps a larger design readable.