Shift Registers

A shift register is a row of flip-flops connected so each stored bit moves one position on every active clock edge. It turns a stream of bits arriving one at a time into values distributed across several register positions.

For a 4-bit right shift, the incoming serial bit enters the most-significant position. The old upper bits move toward the least-significant position. A Verilog concatenation is a compact way to describe the new four-bit value: one new bit joined to three bits from the old register.

Direction names describe where the stored bits move. In a right shift, a bit moves from q[3] toward q[0]. In a left shift, it moves from q[0] toward q[3]. State the MSB and LSB positions before tracing a stream so the direction is unambiguous.

A per-cycle table is often clearer than mental simulation. Write the reset value on row 0, then add one row per clock edge. Copy each old bit into its next position and insert the new serial bit. The table is also a text alternative for a shift-register waveform or diagram.