Reset in Sequential Logic

A flip-flop that has never been given a starting value holds an unknown value. In simulation this shows up as X. Until the first edge writes something real into it, an un-reset flip-flop's output is genuinely undefined — and X values spread: anything computed from an X tends to become X too.

A reset fixes this by forcing a known starting value, usually 0. With a reset, your circuit powers up in a defined state every time instead of depending on chance.

There are two styles of reset. Synchronous reset is applied on the clock edge, inside the same clocked block as the data:

always @(posedge clk) begin
  if (rst) value <= 1'b0;
  else     value <= din;
end

The reset is just the first thing the block checks on each rising edge. Asynchronous reset instead takes effect the instant the reset signal goes high, without waiting for a clock edge; it appears in the sensitivity list as always @(posedge clk or posedge rst).

Both styles are used in real designs, and each has trade-offs around timing and clean startup. Course 1 uses synchronous reset as its default because it keeps every assignment tied to the clock edge, which is easier to reason about while you are learning sequential design. When you see X on a signal that should have a value, a missing or incorrect reset is one of the first things to check.