Verilog Tutorial: From Digital Logic to RTL Design

What Verilog is, where it sits in the toolchain, and how hardware thinking differs.

• Inside the Chip: From Product to Transistor
• The Hardware Design Process
• Where Verilog Fits in the Toolchain
• What Is RTL?
• Theory and Tools: Why You Need Both
• What Is Verilog HDL?
• Optional Local Setup: Icarus Verilog and GTKWave

Gates, truth tables, and boolean expressions — the vocabulary RTL is built from.

• What Is a Digital Circuit?
• Truth Tables
• Combinational Logic
• First Gate: AND
• More Gates: OR, NOT, XOR
• Combining Gates with Internal Signals
• Cleaner Boolean Expressions

Module structure, ports, buses, and how numbers behave in hardware.

• Verilog Module Structure
• Bits, Signals, and Buses
• Numbers in Hardware
• Buses, Widths, and Bit Slices
• `wire` vs `reg` in Verilog
• Verilog Comments, Identifiers, and Keywords
• Four-State Logic: 0, 1, X, and Z

Verilog operators, width and signedness rules, and the pitfalls between them.

• Verilog Operators Overview
• Bitwise vs. Logical Operators in Verilog
• Reduction Operators in Verilog
• Concatenation and Replication in Verilog
• The Conditional (Ternary) Operator in Verilog
• Shift Operators in Verilog

Describing latch-free combinational hardware, and the standard building blocks.

• assign vs. always: Choosing Between Continuous and Procedural Logic
• Avoiding Accidental Latches in Verilog
• if/else for Logic
• case Statements
• MUX Design: Choosing a Style
• First MUX: 2-to-1 Multiplexer
• 4-to-1 MUX
• Basic Decoder
• 3-to-8 Decoder
• Basic Encoder
• Priority Encoder
• Four-Bit Comparator
• Half Adder and Full Adder
• 4-Bit Ripple-Carry Adder
• Mini ALU
• ALU Status Flags
• Building with Submodules

Clocks, flip-flops, reset, and the assignment rules that make sequential logic correct.

• Why Circuits Need Memory
• Clock Edge Intuition
• The D Flip-Flop
• Reset in Sequential Logic
• Blocking vs Non-Blocking Assignments in Verilog
• Registers with Enable
• Counters in Verilog
• Shift Registers
• Registers vs Combinational Logic
• Pipeline Registers and Latency in Verilog
• Linear Feedback Shift Register (LFSR) in Verilog

State diagrams, state tables, and the coding patterns that turn them into hardware.

• FSMs as Stories
• State Diagrams
• The State Register
• Two-Process FSM Pattern in Verilog
• Moore vs Mealy Output Timing
• From Diagram to State Table
• Building a Sequence Detector: State Table to Working Circuit
• A Fixed-Cycle, Timer-Driven Controller

Splitting datapath from control, and composing larger systems from blocks.

• Datapath vs Control: The Split That Makes RTL Systems Readable
• Moving Data on a Bus
• Reusing the ALU in a Datapath
• Register File Basics
• MUXes in a Datapath
• Control Signals
• Clean Hardware Structure

Writing and reading testbenches, and interpreting what a simulator tells you.

• What Is a Testbench?
• How to Read a Simple Testbench
• Reading $display Output
• Corner Cases and Verification Thinking

Finding the first cycle of divergence, reading tool warnings, and thinking about timing.

• How to Read a Verilog Waveform and Find the First Wrong Cycle
• Reading Tool Warnings
• Common Combinational Bugs
• Common Sequential Bugs
• Debugging Sequential Verilog
• Timing Awareness
• AI and Verilog Verification

Standalone guided designs with transferable value.

• 16-Step PWM Generator in Verilog
• Synchronous FIFO in Verilog

What changes when you move from Verilog to SystemVerilog, and what comes next.

• Why Verilog Is Not the End
• logic, always_comb, and always_ff
• Assertions and Interfaces Preview
• Verilog to SystemVerilog Migration Map
• Testing vs. Verification vs. Manufacturing Test