Course Guide

3-to-8 Decoder

How the 2-to-4 decoder pattern scales to three select bits and eight one-hot output lines.

4-Bit Ripple-Carry Adder

How four full adders chain into a 4-bit adder, how the carry ripples from bit 0 to bit 3, and what the final carry-out means.

4-to-1 MUX

Reference for the 4-to-1 multiplexer: two select bits, four data inputs, and how the select value chooses the routed input.

A Fixed-Cycle, Timer-Driven Controller

Reading a written spec for a phase-cycling controller, and implementing it with a built-in safety property, using the dual-block FSM pattern.

AI and Verilog Verification

How to review AI-generated Verilog with selected tests, static warnings, and independent reasoning.

ALU Status Flags

How zero, negative, and carry flags summarize a small ALU result.

always @(*) and the Default-at-Top Pattern

How always @(*) describes combinational logic, and why the default-assignment-at-top pattern is the single most important habit for avoiding an accidental latch.

Assertions and Interfaces Preview

What an SV assertion checks at runtime, and what an interface bundles together, previewed against the capstone signals from Lesson 7.1.

Avoiding Accidental Latches in Verilog

What an inferred latch is, the four coding patterns that cause one inside always @(*), and the two habits that prevent every case.

Basic Decoder

How a binary-to-one-hot decoder works in Verilog, and why default-at-top matters even on a multi-bit output bus.

Basic Encoder

How a one-hot-to-binary encoder works in Verilog, and why it assumes only one input is active at a time.

Bits, Signals, and Buses

A short reference for the smallest data shapes in a digital circuit: bits, named single-wire signals, and the grouped signals that form a bus.

Blocking vs Non-Blocking Assignments in Verilog

A complete, practical guide to = versus <= in Verilog: what each one means, why non-blocking matches real flip-flops, the classic cascade bug, and the two rules that keep you out of trouble.

Building a Sequence Detector: State Table to Working Circuit

Turning a completed state table into a working sequence detector: the clocked state register, the combinational next-state block, and a Mealy-style output line.

Building a Tiny Datapath from Supplied Blocks

A concept-level guide to integrating a register file, MUX, and ALU through readable named connections.

Building the Capstone Controller FSM

A concept-level guide to control_fsm, the capstone controller built on the Module 4 dual-block pattern.

Building the Capstone Datapath

A concept-level guide to wiring the supplied register file and ALU into the capstone datapath.

Building with Submodules

How to instantiate submodules with named port mapping, and why hierarchy is a source-level construct that flattens into one circuit.

Buses, Widths, and Bit Slices

A practical guide to multi-bit signals, explicit bit slices, and avoiding accidental width mismatches in Verilog.

Capstone Readiness: What to Check Before You Start

A concept-level guide to the patterns worth confirming before starting the Tiny Calculator Engine.

case Statements

How case describes multi-way selection in Verilog, and why a default branch matters even when every value seems already listed.

Clean Hardware Structure

How lint warnings expose unused signals, undriven outputs, width mismatches, and other structural risks before integration.

Cleaner Boolean Expressions

Recognize simple redundant Boolean terms and equivalent rewrites without a full minimization method.

Clock Edge Intuition

How a clock drives sequential logic, why a flip-flop only samples on the rising edge, and why mid-cycle input changes are invisible.

Combinational Logic

Reference for combinational logic in Verilog: outputs set only by current inputs, the gate operators, and how to debug a failing combinational design.

Combining Gates with Internal Signals

Reference for wire declarations in Verilog: naming an intermediate signal so one gate output can feed another gate input.

Common Combinational Bugs

The four bug classes behind most combinational mistakes — wrong operator, missing default, wrong case item, and width mistake — and how each shows up in failing output.

Common Sequential Bugs

The four bug classes behind most sequential mistakes — missing reset, wrong assignment type, wrong clock edge, and enable bug — and how each shows up in a waveform.

Control Signals

How small control wires coordinate register writes, MUX paths, and ALU operations in an RTL datapath.

Corner Cases and Verification Thinking

How to choose a compact test set that covers boundaries, controls, and unusual operating conditions.

Counters in Verilog

How a binary counter stores, increments, holds, resets, and wraps across clock edges.

Datapath vs Control: The Split That Makes RTL Systems Readable

A practical guide to separating stored and transformed values from the control decisions that move them through an RTL system.

Debug and Fix Project Slice

A repeatable workflow for locating the first divergence, fixing a planted RTL bug, and recording root cause.

Debugging Final RTL Failures

A compact evidence-first protocol for isolating and repairing an integrated RTL failure.

Debugging Sequential Verilog

A symptom-first guide to wrong assignment type, missing reset, wrong clock edge, and width mismatch.

First Gate: AND

Reference for the AND gate in Verilog: the & operator, its truth table, and how a continuous assignment maps it to hardware.

First MUX: 2-to-1 Multiplexer

Reference for the 2-to-1 multiplexer: select-driven data routing and the conditional operator that expresses it.

Four-Bit Comparator

How a comparator produces equality, greater-than, and less-than flags for two multi-bit values.

From Diagram to State Table

How to turn a sequence-detector state diagram into a complete state table, including the transitions where a partial match has to reset.

FSMs as Stories

The three ideas every finite state machine is built from — state, transition, and output — explained through everyday examples before any diagram or code.

Half Adder and Full Adder

What half adders and full adders compute, and why the full adder is the building block for every wider adder.

How Project Slice Submission Works

What a project slice actually checks, and a process for designing a new sequence detector from a written spec instead of a fill-in-the-blank scaffold.

How to Read a Simple Testbench

The parts of a supplied testbench — DUT, stimulus, expected values, and checks — and how to trace a failing line back to its input.

if/else for Logic

Why if/else inside always @(*) describes a multiplexer, and why every branch must assign the output.

Inside the Chip: From Product to Logic Circuit

A short reference for the layers inside a digital product, from the device shell down to the network of logic gates this course teaches.

Integrating the Capstone: Compile First, Run Second

A concept-level guide to wiring tiny_calc_top and the compile-first discipline Lesson 7.5 uses.

logic, always_comb, and always_ff

How SystemVerilog logic, always_comb, and always_ff map onto the Verilog wire, reg, always @(*), and always @(posedge clk) you already know.

Mini ALU

What an ALU is, how a small opcode selects between arithmetic and logic results, and why an ALU is really a MUX of operations.

Module 1 Checkpoint — Further Reading

Reference for the Module 1 Checkpoint: skills you demonstrated by predicting, simulating, and reflecting on a combinational circuit across Lessons 1.1 through 1.8.

Module 2 Checkpoint — Further Reading

Reference for the Module 2 Checkpoint: skills you demonstrated by building combinational blocks, avoiding accidental latches, and reading a simple testbench across Lessons 2.1 through 2.14.

Module 3 Checkpoint Review

A quick review of clocked storage, non-blocking assignments, counters, shift registers, waveforms, and the RTL definition.

Module 4 Checkpoint Review

A quick review of the dual-block FSM pattern, default-case recovery, Moore-versus-Mealy output timing, and the project-slice submission format.

Module 5 Review: Datapath and Control

A compact review of data routes, control decisions, widths, hierarchy, and structural warnings.

Module 6 Checkpoint

A compact review of first-divergence debugging, defensive FSM recovery, and datapath write control.

Moore vs Mealy Output Timing

The difference between Moore-style output (depends on state only) and Mealy-style output (depends on state and input), and why this course defaults to Moore.

More Gates: OR, NOT, XOR

Reference for the Verilog OR (|), NOT (~), and XOR (^) operators and the truth-table pattern each one produces.

Moving Data on a Bus

How MUX-selected buses route one data source through a datapath at a time.

MUX Design: Choosing a Style

Ternary, if/else, and case all describe the same multiplexer hardware — how to choose the style that reads clearest and scales best.

MUXes in a Datapath

How control signals select the data path into an ALU, a write-back destination, or another datapath connection.

Next Step: SystemVerilog Verification Essentials

The honest status of Course 2 and what it will cover when it ships.

Numbers in Hardware

How Verilog vector widths and hex literals work, and why a fixed-width addition can overflow and truncate silently.

Planning a Controller-Plus-Datapath Project Slice

How to separate a controller event from a capture datapath and explain a design tradeoff without exposing assessment answers.

Priority Encoder

How a priority encoder defines an output when more than one request input is active.

Reading $display Output

How to read a failing $display line and use a pattern across several lines to predict a bug class before opening the RTL.

Reading the Capstone Block Diagram

A concept-level guide to the datapath/control coloring and named signals on the capstone block diagram.

Reading the Tiny Calculator Engine Spec

A concept-level guide to turning the capstone spec document into a short requirements checklist.

Reading Tool Warnings

A compact guide to classifying inferred-latch, width-mismatch, unused-or-undriven, and combinational-loop warnings, with a worked fix for each.

Reading Waveforms to Find the First Cycle of Divergence

Why the first cycle where a waveform stops matching its expected signal is almost always more useful than any later cycle, and how to find it quickly.

Register File Basics

How a small register file combines addressed storage, clocked writes, and combinational reads.

Registers vs Combinational Logic

How sensitivity lists distinguish immediate combinational behavior from clocked storage.

Registers with Enable

How a multi-bit register is built from parallel flip-flops, how the width comes from the vector declaration, and what an enable signal does.

Reset in Sequential Logic

Why an un-reset flip-flop simulates as an unknown X, what a reset gives you, and the difference between synchronous and asynchronous reset.

Reusing the ALU in a Datapath

How named module-port mappings let an ALU become a reusable block inside a larger RTL datapath.

Shift Registers

How serial bits move through a multi-bit register one position per clock edge.

State Diagrams

How to read a state diagram — circles as states, arrows as transitions, labels as input conditions — and why a reset state matters.

Submitting the Tiny Calculator Engine RTL Proof

A field-by-field guide to the final capstone bundle, expert review, and private-to-public proof flow.

Testing vs. Verification vs. Manufacturing Test

Three distinct activities that get confused in casual conversation about chip design: testing, verification, and manufacturing test.

The D Flip-Flop

The most basic memory element in digital design: what a D flip-flop does, the Verilog idiom for it, and why clocked logic uses non-blocking assignment.

The Dual always-Block FSM Pattern

Why every FSM in this course is written as exactly two always blocks — a clocked state register and a combinational next-state block — and why single-block FSMs are off the menu.

The Hardware Design Loop

A short reference for the repeating engineering loop used across hardware design: specify, describe, simulate, compare, debug, and package proof.

The State Register

The state register is the one clocked block in an FSM — a synchronous-reset flip-flop pattern applied to a multi-bit state value.

Theory and Tools: Why You Need Both

A short reference for how design theory and verification tools share responsibility for proving that a digital circuit actually works.

Timing Awareness

A beginner guide to propagation delay and the setup and hold windows around a flip-flop sampling edge.

Tiny Calculator Engine Self-Review

Repair routes for each of the eight advisory capstone evidence checks.

Truth Tables

Reference for reading and building truth tables: input columns, output columns, and counting the rows.

Verilog Module Structure

Reference for the parts that form every Verilog module: the module keyword, the port list, the body, and endmodule.

Verilog to SystemVerilog Cheat Sheet

Where to find the one-page Verilog-to-SystemVerilog reference, and what it covers.

What Is a Digital Circuit?

Reference for combinational logic: how logic gates transform input bits to output bits, and why truth tables describe that behavior.

What Is a Testbench?

The three regions every supplied SystemVerilog testbench in this course follows: DUT instantiation, clock and stimulus, and checks and reporting.

What Is RTL?

A first formal definition of Register Transfer Level using registers, combinational logic, and clocked data movement.

What Makes RTL Proof More Than a Passing Checker

A concept-level guide to the three attributes that distinguish a strong RTL Proof from a weak one.

When assign Gets Messy

Why larger combinational decisions read cleaner as a procedural always @(*) block instead of a single nested assign expression.

Where Verilog Fits in the Toolchain

A short reference for how Verilog hardware descriptions move through simulators, waveforms, and synthesis on the way to a working circuit.

Why Circuits Need Memory

The difference between combinational circuits that forget and sequential circuits that remember, and the words and keywords that signal stored state.

Why Verilog Is Not the End

What SystemVerilog adds on top of the Verilog RTL design skills Course 1 taught.

Writing an Honest Verification Summary

How to explain tested behavior, corner cases, warnings, and limits without overstating a finite regression.