Skip to article
Silicon Chip Academy Verilog Tutorial Continue to Verilog Module Structure

Modules, Signals, and Numbers

Verilog Comments, Identifiers, and Keywords

The lexical rules classic Verilog code follows: comment syntax, legal identifier names, case sensitivity, and the reserved keywords you cannot use as signal names.

2 min read · Updated

Before reading a module's behavior, it helps to know the small lexical rules every line of classic Verilog follows.

Comments

Verilog supports the same two comment forms as C:

// a single-line comment, to the end of the line
/* a block comment
   that can span multiple lines */

Block comments do not nest — a /* inside an already-open block comment has no special effect, and the comment still ends at the next */.

Identifiers

A plain (simple) identifier — a signal, module, or variable name — must start with a letter or underscore. After that first character, letters, digits, $, and _ are all legal. Verilog identifiers are case-sensitive: data and Data name two different signals — a common source of confusing "undeclared identifier" errors when a typo only changes case.

Identifier Legal? Why
data_in Yes Starts with a letter; letters and underscore after
q2 Yes Starts with a letter
2to1_mux No Starts with a digit
$reg_a No Starts with $ — reserved for system tasks/functions like $display, not a legal leading character for an ordinary identifier
reg_a$1 Yes $ is legal after the first character
my-signal No Hyphen is not a legal identifier character

An escaped identifier — a backslash followed by the name and terminated by whitespace, such as \2to1-mux — can contain otherwise-illegal characters, including a leading digit. It is rarely used in hand-written RTL and mostly appears in tool-generated netlists.

Keywords

Keywords are reserved words the language grammar itself uses — module, endmodule, input, output, wire, reg, always, assign, begin, end, if, else, case, parameter, and roughly a hundred others. A keyword cannot be reused as a signal, module, or variable name.

module wire (input a, output y);   // illegal: "wire" is a keyword, not a valid module name

This occasionally surprises engineers moving from a language with fewer reserved words. Vector-bit names like a1, index variables like i, and prefixes like wire_a are all legal precisely because they are not exact keyword matches.

Where to go from here

Verilog Module Structure puts these rules to use in the smallest complete unit of Verilog — a module with ports. wire vs reg covers the two most common declaration keywords in more depth.