Technical review status

This page is generated from the repository, not written by hand. It reports what has actually been checked on the Verilog Tutorial, so it cannot drift away from the truth or quietly go stale.

Two different claims

They are not the same thing, and we keep them separate on purpose.

Example verified: An automated check extracts the complete example from the page itself, compiles it with Icarus Verilog, runs it, and requires the simulator's output to match the output printed on the page line for line. It runs on every change to the article. This proves the code compiles and does what the page says it does. It proves nothing about whether the surrounding explanation is good engineering advice.
Reviewed by a person: A named reviewer read the exact published wording and recorded a completed review against that specific version. If the page is edited afterwards, the record stops applying and the page returns to unreviewed until someone reviews it again.

Current status

Of 110 tutorial pages, 20 carry an automatically verified example and 0 have a recorded human technical review.

Tutorial pages with an automatically verified example or a recorded human review
Page	Example verified	Reviewed by a person
What Is Verilog HDL?	Yes	Not yet
Verilog Module Structure	Yes	Not yet
Numbers in Hardware	Yes	Not yet
`wire` vs `reg` in Verilog	Yes	Not yet
Four-State Logic: 0, 1, X, and Z	Yes	Not yet
Verilog Operators Overview	Yes	Not yet
Bitwise vs. Logical Operators in Verilog	Yes	Not yet
Reduction Operators in Verilog	Yes	Not yet
Concatenation and Replication in Verilog	Yes	Not yet
The Conditional (Ternary) Operator in Verilog	Yes	Not yet
Shift Operators in Verilog	Yes	Not yet
Avoiding Accidental Latches in Verilog	Yes	Not yet
Blocking vs Non-Blocking Assignments in Verilog	Yes	Not yet
Pipeline Registers and Latency in Verilog	Yes	Not yet
Linear Feedback Shift Register (LFSR) in Verilog	Yes	Not yet
Two-Process FSM Pattern in Verilog	Yes	Not yet
Datapath vs Control: The Split That Makes RTL Systems Readable	Yes	Not yet
How to Read a Verilog Waveform and Find the First Wrong Cycle	Yes	Not yet
16-Step PWM Generator in Verilog	Yes	Not yet
Synchronous FIFO in Verilog	Yes	Not yet

What we are not claiming

SkillLift Labs has no named public expert to point at, and we are not going to invent one. Articles are published under the organisation's name.
A page with a verified example is not certified correct. Working code can still sit beside a bad explanation.
Nothing here has been through external peer review, and we do not describe it as though it has.

If something on a tutorial page is wrong, please tell us — the report a technical error form goes to a person, not a queue.