Testing vs. Verification vs. Manufacturing Test

These three terms get used interchangeably in casual conversation — digital-logic textbooks often say "testing" for design checking and chip checking alike — but they answer different questions and are done by different people at different points in a real project.

Directed testing ("I tested it") means one or more simulations ran without errors on cases someone chose by hand. It is useful, but each run is one data point — it says nothing about scenarios you did not think to run, and it is one technique used inside verification, not a separate activity from it.

Verification ("it's verified") means enough scenarios were covered — directed and constrained-random — that the design has earned broader confidence than a small set of directed tests gives, not proof that no bug exists anywhere. It starts from a plan listing what the specification requires, and coverage records which planned scenarios the tests have actually exercised. Course 2 teaches this: assertions, reusable testbenches, and constrained-random stimulus that build toward that broader confidence.

Manufacturing test is a separate discipline entirely: checking a physical, fabricated chip for defects introduced during manufacturing. It has nothing to do with whether the design itself is correct — a perfectly verified design can still come off the fabrication line with a physical defect, and manufacturing test is the discipline that catches that. A common way to model such a defect is a wire stuck at 0 or stuck at 1 in one chip while every other chip works.

Course 1 gave you simulation and directed testing, and started verification thinking with Lesson 6.8's corner cases, later Module 7's debug evidence and the capstone's verification summary. Course 2 turns that thinking into a systematic verification methodology. Manufacturing test is its own field, mentioned here only so the three are not confused with each other.