Module 1 Checkpoint — Further Reading

Module 1 Checkpoint — Further Reading

The Module 1 Checkpoint confirms that you can predict, simulate, and reflect on a combinational circuit — the same skills you practised in Lessons 1.1 through 1.8.

What you demonstrated:

• Reading a truth table and predicting a gate's output before running it.
• Running synthesisable Verilog against a supplied checker and interpreting simulation output.
• Articulating why the circuit behaves the way it does.

If any stage felt shaky, revisit the lesson it draws from:

Up next: Module 2 expands your combinational Verilog toolkit — always @(*), if/else, case, arithmetic, hierarchy, and latch-safe design. Module 3 is where clocked state begins: flip-flops, registers, counters, and shift registers.