What Is a Testbench?

A testbench is a non-synthesizable module that drives inputs into a design and checks its outputs against expected values. This course supplies the testbenches; you read them. Course 2 teaches you to write your own.

Every supplied testbench follows the same three-region shape.

DUT instantiation. One line connects your design — the DUT, or design under test — to the testbench's own signals. This is the only place the testbench actually touches your module by name.

Clock and stimulus. A clock generator toggles clk on a fixed period, usually with a single always #N clk = ~clk; line. Stimulus lines assign values to the DUT's inputs, in the order the test plan needs them.

Checks and reporting. Comparison lines check an output against an expected value, and $display lines print the result — typically labelled PASS or FAIL, along with the input case, the expected value, and the value the design actually produced.

Learning to spot these three regions on sight is what lets you trust a testbench you did not write, and later, in Course 2, write testbenches of your own.