First Gate: AND

Reference for the AND gate in Verilog: the & operator, its truth table, and how a continuous assignment maps it to hardware.

Updated 2026-06-05

The AND gate outputs 1 only when all of its inputs are 1; for any other combination the output is 0. Its two-input truth table has four rows, and only the 1 1 row produces a 1.

In Verilog the bitwise AND operator is &. Placing it inside a continuous assignment tells the synthesizer to build an AND gate: the output wire continuously follows the AND of the input wires, with no clock and no ordering. This is your first concrete link between an operator and a piece of hardware.

If a circuit using AND misbehaves, check the operator first. A single bitwise & means AND; the logical && and the other gate operators describe different behavior and different truth tables.