The D Flip-Flop

A D flip-flop is the simplest memory element in digital design. It captures its data input d on the rising clock edge and holds that value on its output q until the next edge. Between edges the output stays put, no matter what the input does.

In Verilog you describe it with a clocked block:

always @(posedge clk) begin
  q <= d;
end

The header always @(posedge clk) says "run this on every rising clock edge." Inside, q <= d copies the input onto the output. Because the block is clocked, q must be declared as reg — it holds a value between edges rather than tracking its input continuously the way an assign net does.

Notice the <= operator. That is the non-blocking assignment, and it is the correct choice for clocked logic. Non-blocking assignments schedule all their updates to happen together at the edge, which matches real hardware where every flip-flop samples at the same instant. Lesson 3.5 goes deeper on why this matters; for now, the habit is simple: inside always @(posedge clk), always use <=.

Because a flip-flop only samples on the edge, mid-cycle changes on d are invisible. If you feed a flip-flop an input that toggles several times within one clock cycle, the output still takes just one value — whatever d happened to be at the rising edge.