Reading the Capstone Block Diagram

The capstone block diagram extends the Module 5 datapath/control anchor image to three named submodules: the register file and ALU in green (datapath), the FSM controller in orange (control).

Every wire crossing between the two regions is a control decision, not a data value:

• reg_write_en leaves the FSM and enters the register file's write-enable pin — it decides whether a write happens, not what is written.
• alu_op leaves the FSM and enters the ALU — it decides which operation runs, not the operand values themselves.
• done leaves the FSM as a status pulse for whatever calls the top-level module.

Everything that stays inside the green datapath region — rs1_data, rs2_data, result — carries an actual 4-bit value.

This diagram is a design plan, not a wiring-correctness check. Whether every connection actually compiles and produces the right value is proven where it is real: Lesson 7.3's controller-stub testbench and Lesson 7.5's integrated system, not in a diagram tool.