Reading the Capstone Block Diagram

The capstone block diagram extends the Module 5 datapath/control anchor image. The register file, the immediate MUX and the ALU sit in green (datapath); the FSM controller sits in orange (control).

Read each wire from the block that drives it to the block it enters, then ask what it carries. A value being stored or computed is datapath; a decision is control, even when it is a single bit. On this diagram, every wire that crosses from the control region into the datapath is a decision:

• reg_write_en leaves the FSM and enters the register file's write enable — it decides whether a write happens, not what is written.
• alu_op leaves the FSM and enters the ALU — it decides which operation runs, not the operand values themselves.
• done leaves the FSM as a status pulse for whatever calls the top-level module.

The wires that stay inside the green region — rs1_data, rs2_data, alu_b and result — carry actual 4-bit values. Two more inputs enter the datapath from outside both regions: the immediate value imm4 (a value) and its select use_imm (a decision). The testbench drives both in Lesson 7.3; in Lesson 7.5 the top-level module's load path drives them.

This diagram is a design plan, not a wiring-correctness check, and it leaves some wires out, such as the register addresses. Whether every connection actually compiles and produces the right value is proven where it is real: Lesson 7.3's controller-stub testbench and Lesson 7.5's integrated system, not in a diagram tool.