Timing Awareness

Real gates and wires are not instant. Propagation delay is the time between an input change and the resulting output change through physical logic and wiring.

A flip-flop samples its data input at an active clock edge. For dependable capture, data must be stable during two short intervals:

• The setup window is immediately before the active edge.
• The hold window is immediately after the active edge.

A data transition inside either window is too close to the sampling event for dependable capture. A transition well before the setup window is safe only if data then remains stable through the edge and the hold window.

Functional simulation checks the RTL behavior for selected input sequences under an idealized timing model. Timing-aware implementation tools answer the separate question: can the physical circuit deliver stable data to each sampling element soon enough?

At this stage, focus on the timeline intuition. Mark the active edge, shade the setup and hold windows, and compare the data transition with that shaded interval.