Integrating the Capstone: Compile First, Run Second

tiny_calc_top instantiates your own Lesson 7.3 tiny_calc_datapath and your own Lesson 7.4 control_fsm directly, unchanged — it does not rebuild either one's internal wiring. Your job is the connections between them: control_fsm's two outputs feed a supplied load-or-compute mux, and that mux's output reaches tiny_calc_datapath's inputs.

Compile first, run second separates syntax and elaboration errors from behavioral failures. An invalid port name is a compile error. A disconnected port or a connection to the wrong same-width wire can still compile, so a clean compile does not establish correct behavior.

Trace each blank by port direction, width and role. An output drives a surrounding wire; an input receives one. Follow the supplied selection expressions to decide whether a port needs a source value or the selected value. The load mode adds an immediate operand to register 0's zero, so the calling protocol reserves register 0 and loads only registers 1 and 2 while idle.

done proves a write was requested this cycle, not that it has already landed. The register file's actual write completes at the edge ending WRITEBACK. Before that edge, the destination still holds its previous value, which may happen to equal the new result. Check both sides of the edge and confirm that idle, FETCH and EXECUTE preserve storage. This timing describes this capstone's protocol; a different controller could define its completion signal differently.

Your own passing Lesson 7.3 and 7.4 code is supplied automatically for this lesson — you are not re-typing either one, only wiring the connections that make them work together.