SystemVerilog Bridge
Verilog to SystemVerilog Migration Map
A one-page mapping from the Verilog constructs you already use to their SystemVerilog equivalents, and why each one changed.
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SystemVerilog is a superset of Verilog, so Verilog code carries over unchanged, with one catch: SystemVerilog
reserves extra words, such as logic, bit and interface, and Verilog code that used one as a signal name
must rename it. What it adds are constructs that make intent explicit and make verification scale. This page maps the ones you meet first to
what you already know.
Types
| Verilog | SystemVerilog | Why it changed |
|---|---|---|
wire |
logic |
For a single-driver signal: one type, instead of choosing wire or reg based on how you happen to assign it. |
reg |
logic |
Same replacement — logic covers both, so declaring a signal no longer requires knowing in advance whether it will be driven by assign or an always block. |
logic is a naming and clarity change, not new hardware behaviour. Its one limit is the number of drivers:
one assign, or procedural code, but not several continuous drivers and not a mix of the two. wire has not
gone away. A net that genuinely needs more than one driver — a shared bus, a
tri-state line — still declares wire. logic is the common default, not a replacement for every net type.
Procedural blocks
| Verilog | SystemVerilog | Why it changed |
|---|---|---|
always @(*) |
always_comb |
States combinational intent explicitly, so a tool can flag a block that looks combinational but leaves an output unassigned on some path. |
always @(posedge clk) |
always_ff @(posedge clk) |
States clocked intent explicitly, so a tool can warn when the block has no clock edge to act on. |
That first row is worth pausing on. In Verilog, an unassigned path inside always @(*) is legal code that
infers a latch; a tool may warn, but it cannot know you wanted no storage. always_comb declares that you did
not, so the SystemVerilog standard asks tools to warn about the latch — the
latch-avoidance habit does not
change, but the tool now knows your intent.
Verification additions
These belong to verification work rather than RTL design, and they are where SystemVerilog earns its reputation.
| Construct | What it does |
|---|---|
assert property (...) |
States a rule once; the simulator checks it automatically, at every clock edge it names, instead of a human checking it by hand. |
interface |
Bundles related signals — like a small bus — so they connect and travel together as one named group. |
enum |
Makes state names a type: ordinary assignments to a signal of that type use those names; a raw code needs an explicit cast. |
What did not change
- Module ports, instantiation, and hierarchy work the same way.
- Non-blocking (
<=) versus blocking (=) assignment discipline is unchanged. - The default-assignment-at-top habit still applies inside
always_comb.
Keep this page open in a tab when you write your first SystemVerilog testbench. It is a reference, not new material — everything here maps onto Verilog you already understand.