SystemVerilog Bridge
Verilog to SystemVerilog Migration Map
A one-page mapping from the Verilog constructs you already use to their SystemVerilog equivalents, and why each one changed.
2 min read · Updated
SystemVerilog is a superset of Verilog: everything you have written so far still compiles. What it adds are constructs that make intent explicit and make verification scale. This page maps the ones you meet first to what you already know.
Types
| Verilog | SystemVerilog | Why it changed |
|---|---|---|
wire |
logic |
For a single-driver signal: one type, instead of choosing wire or reg based on how you happen to assign it. |
reg |
logic |
Same replacement — logic covers both, so declaring a signal no longer requires knowing in advance whether it will be driven by assign or an always block. |
logic follows the same single-driver rule reg did: it is a naming and clarity change, not new hardware
behaviour. wire has not gone away. A net that genuinely needs more than one driver — a shared bus, a
tri-state line — still declares wire. logic is the common default, not a replacement for every net type.
Procedural blocks
| Verilog | SystemVerilog | Why it changed |
|---|---|---|
always @(*) |
always_comb |
States combinational intent explicitly, so a tool can flag a block that looks combinational but leaves an output unassigned on some path. |
always @(posedge clk) |
always_ff @(posedge clk) |
States clocked intent explicitly, so a tool can flag a signal written outside a clocked block. |
That first row is worth pausing on. In Verilog, an unassigned path inside always @(*) silently infers a
latch and you find out from a synthesis warning. In SystemVerilog, always_comb lets the tool say so
directly — the latch-avoidance habit
does not change, but the feedback arrives earlier.
Verification additions
These belong to verification work rather than RTL design, and they are where SystemVerilog earns its reputation.
| Construct | What it does |
|---|---|
assert property (...) |
States a rule once; the simulator checks it automatically, every cycle, instead of a human checking it by hand. |
interface |
Bundles related signals — like a small bus — so they connect and travel together as one named group. |
enum |
Names state machine states directly instead of encoding them as raw bit patterns. |
What did not change
- Module ports, instantiation, and hierarchy work the same way.
- Non-blocking (
<=) versus blocking (=) assignment discipline is unchanged. - The default-assignment-at-top habit still applies inside
always_comb.
Keep this page open in a tab when you write your first SystemVerilog testbench. It is a reference, not new material — everything here maps onto Verilog you already understand.