Concept Review
Quick-reference articles for Verilog RTL Foundations. Use these alongside lessons to reinforce key ideas.
- verilog
assign vs. always: When to Use Each
A quick reference for choosing between continuous assignment (assign) and procedural blocks (always) in synthesizable RTL.
- verification
Reading VCD Waveforms
How to interpret VCD timeline output from iverilog simulations — signal names, time steps, and value changes.
- systemverilog
Verilog to SystemVerilog: A Quick Migration Map
A one-page mapping from Verilog constructs to their SystemVerilog equivalents, for use starting in Course 2.