verification module-3module-6
Reading VCD Waveforms
How to interpret VCD timeline output from iverilog simulations — signal names, time steps, and value changes.
Updated 2026-04-30
What is a VCD file?
Value Change Dump (VCD) is a standard ASCII format for recording signal values over simulation time. iverilog produces VCD when you include $dumpfile / $dumpvars in your testbench.
initial begin
$dumpfile("sim.vcd");
$dumpvars(0, tb_and_gate); // dump all signals in tb_and_gate
// ... stimulus
$finish;
endVCD file structure
$timescale 1ns $end // time unit for #N delays
$scope module tb_and_gate $end
$var wire 1 ! a $end // signal a, ID !
$var wire 1 " b $end // signal b, ID "
$var wire 1 # y $end // signal y, ID #
$upscope $end
$enddefinitions $end
#0 // time = 0
0! 0" 0# // a=0, b=0, y=0
#10 // time = 10ns
1! // a changes to 1
#20
1" // b changes to 1 → y goes to 1
1#Reading the timeline
Each #N marks a time step. The lines following it show only the signals that changed (VCD is delta-encoded). A missing signal means its value is unchanged from the previous time step.
Scalar value changes
| Syntax | Meaning |
|---|---|
0! |
signal with ID ! is 0 |
1! |
signal with ID ! is 1 |
x! |
unknown |
z! |
high-impedance |
Vector (bus) value changes
b1010 $ // multi-bit signal with ID $ = 4'b1010Mapping IDs back to signal names
The $var declarations at the top of the file map short IDs (like !, ", #) to human-readable signal names. Use the WaveformViewer in the SkillLift player to see this mapping automatically.
Common pitfalls
- No VCD output? Check that
$dumpfileand$dumpvarsare inside aninitialblock and that$finishis called. - Signals show
xat time 0? Normal — signals are uninitialized until driven. - Missing signals? Increase the depth argument to
$dumpvars(depth, module). Use0to dump all levels. - VCD too large? Narrow the dump window: use
$dumpon/$dumpoffaround the region of interest.