Verilog to SystemVerilog: A Quick Migration Map

The core idea

SystemVerilog is a superset of Verilog: everything you wrote in Course 1 still compiles. SystemVerilog adds new constructs that make intent explicit and make verification scale. This page maps the handful you previewed in Lessons B.1-B.5 to what you already know from Verilog.

Types

Verilog	SystemVerilog	Why it changed
wire	logic	For a single-driver signal: one type instead of choosing wire vs. reg by assignment style.
reg	logic	Same replacement — logic covers both, so declaring a signal no longer requires knowing in advance whether it will be driven by assign or an always block.

logic cannot be driven by more than one continuous/procedural source at once, same rule as reg — it is a naming and clarity change for single-driver signals, not a new hardware behavior. wire has not gone away: a net that genuinely needs more than one driver (a shared bus, a tri-state line) still declares wire, so logic is the common default, not a full replacement for every net type.

Procedural blocks

Verilog	SystemVerilog	Why it changed
always @(*)	always_comb	States combinational intent explicitly; a tool can flag a block that looks combinational but is missing an assignment on some path.
always @(posedge clk)	always_ff @(posedge clk)	States clocked intent explicitly; a tool can flag a signal written outside a clocked block.

Verification additions (Course 2 territory)

Construct	What it does
assert property (...)	States a rule once; the simulator checks it automatically, every cycle, instead of a human checking it by hand.
interface	Bundles related signals — like a small bus — so they connect and travel together as one named group.
enum	Names FSM states directly instead of encoding them as raw bit patterns.

What did not change

• Module ports, instantiation, and hierarchy work the same way.
• Non-blocking (<=) vs. blocking (=) assignment discipline is unchanged.
• The default-at-top latch-avoidance habit from Module 2 still applies inside always_comb.